The memory available to a microprocessor commonly includes special high speed memory referred to as cache memory or simply cache. Cache memory comprises an array of individual memory cells, each memory cell adapted to store one bit of data. A number of memory cells are arranged in a column connected by two conductors referred to as a bit line pair. The memory arrangement includes a number of such columns of memory cells. Data is written to or transferred from a particular memory cell in the arrangement via the bit line pair associated with the column of memory cells in which the particular memory cell is included. A voltage signal in a "high" range on one bit line of the bit line pair with a "low" voltage signal on the opposite bit line represents one logical state. A voltage signal in a "high" range on the opposite bit line and corresponding "low" voltage signal on the one bit line represents the opposite logical state. The memory cells are connected in rows by word lines which are used to activate a particular memory cell in a column and allow data, that is, one logical state or the other, to be written to or transferred from the particular cell.
A write driver is used to control the charge state of the bit line pairs during a write operation to a memory cell within a column. The write driver comprises a circuit connected to the bit line pair which causes the bit lines in the pair to have the desired voltage state representing the data to be stored in a memory cell. A column decoder and sense amplifier are also connected to the bit line pair for reading data which has been stored in the memory cells. A bit line precharge circuit commonly accompanies the write driver circuit. The bit line precharge circuit operates to charge both lines of the bit line pair prior to a read or write operation.
In a read operation, the logical high charge must be maintained on one of the bit lines of the pair, while the charge state on the opposite bit line is allowed to decay through the selected memory cell. Once a minimum voltage differential has developed between the two bit lines, the sense amplifier is activated to convert the differential voltage signals appearing on the bit lines to a true digital signal.
In the prior art, the charge on one bit line is maintained only through a small transistor in the selected memory cell. However, the capacitance associated with the bit line and junction capacitance associated with the transfer gate device of each memory cell in the column can cause the charge on the bit line to decay during a long read operation. This decay in the charge on the bit line which is intended to be maintained at a high level, reduces the voltage differential between the two bit lines of the bit line pair and may interfere with the operation of the sense amplifier. That is, a reduced voltage differential on the bit line pair during the read operation may cause the sense amplifier to incorrectly sense the data appearing on the bit line pair, and produce an incorrect result.